The second edition of this book has been thoroughly updated to cover new developments in the field and includes new diagrams and end-of-chapter exercises. It will also be accompanied by a lecturer and student web site which will contain solutions to exercises, further exercises, PowerPoint slides and all the source code used in the book.
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This text was developed to serve as an introduction to computing systems. Author : Arthur B. Author : Ivan Tomek Publisher: W. Freeman ISBN: Category: Computers Page: View: Read Now » With a central focus on the computer as an organized hierarchy of functions--from hardware fundamentals to the elements of high-level software--this substantially revised version of Introduction to Computer Organization offers a wealth of interactive learning support through extensive examples, exercises, and accompanying lab experiments.
Six appendixes, an annotated bibliography, a glossary, and a complete index help the learning process as well. Author : A. Author : Michel Dubois Publisher: Cambridge University Press ISBN: Category: Computers Page: View: Read Now » Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future.
In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems.
All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. Author : M. Morris Mano Publisher: Pearson ISBN: UOM Category: Computers Page: View: Read Now » Dealing with computer architecture as well as computer organization and design, this fully updated book provides the basic knowledge necessary to understand the hardware operation of digital computers.
Author : John P. Computer Systems Organization -- Parallel architecture. The author has carefully arranged the chapters and topics using Education Technology and Courseware Engineering Principles, with proper planning to help self-paced as well as guided learning.
Large numbers of examples, solved problems and exercises have been incorporated to help students strengthen their base in the subject. A number of multiple choice questions have been included with answers and explanatory notes.
This logical address is added to the shifted contents of the seg- ment register segment base address to give a physical memory address. Address indirection in the X86 family can be obtained using the content of a base pointer register BPR , the content of an index register, or the sum of a base register and an index register. Using the naming convention introduced before, these instruction types are data movement, arithmetic and logic, and sequencing control transfer.
Data movement instructions in the X86 family include mainly four subtypes. A sample of these instructions is shown in Table 3. These are addition, subtraction, multiplication, division, and logic instructions.
A sample of the arithmetic instructions is shown in Table 3. In addition, the X86 family has a set of shift and rotate instructions. A sample of these is shown in Table 3.
These are conditional, iteration, interrupt, and unconditional. Processor control instructions in the X86 family include mainly three subtypes. Having introduced the basic features of the instruction set of the X86 processor family, we now move on to present a number of programming examples to show TABLE 3. The examples presented are the same as those presented at the end of Chapter 2. Example 3 Adding numbers stored at consecutive memory locations starting at location , the results should be stored in memory location FLAG is a memory variable used to indicate whether the list has been sorted or not.
The register CX is used as a coun- ter with the Loop instruction. The Loop instruction decrements the CX register and branch if the result is not zero. The register CX is used as a counter with the loop instruction. Therefore, care should be made to avoid altering the value of the IP register. The top of the stack is thus saved to a temporary variable TEMP at procedure entry and restored before exit. Assembly language provides easier to use symbolic representation, in which an alphanumeric equivalent to machine language is used.
There is a one-to-one corre- spondence between assembly language statements and machine instructions. An assembler is a program that accepts a symbolic language program source program and produces its machine language equivalent target program. In some applications, small por- tions of a program that are heavily used may need to be written in assembly language. Programming in assembly can result in machine code that is smaller and faster than that generated by a compiler of a high-level language.
Assembly pro- grammers have access to all the hardware features of the target machine that might not be accessible to high-level language programmers. In addition, learning assem- bly languages can be of great help in understanding the low level details of computer organization and architecture. In this chapter we provided a general overview of assembly language and its programming.
The programmer view of the X86 Intel microprocessor family of processors was also introduced as a real-world example. Examples were then presented showing how to use the X86 instruction set in writing sample programs similar to those presented in Chapter 2. What is the difference between each of the following pairs? Compilers and assemblers.
Source code and target code. Mnemonics and hexadecimal representation. Pseudo instructions and instructions. Labels and addresses. Symbol table and opcode table. Using the assembly language of the simple processor in Section 3. Swap two numbers.
Logical OR. Negation 3. Obtain the machine language code of the multiplication assembly program given in Section 3. With the great advances in high-level languages and compilers, some people argue that assembly language is not important anymore. Give some argu- ments for and against this view. Write a subroutine using the X86 instructions that can be called by a main program in a different code segment.
The subroutine will multiply a signed bit number in CX by a signed 8-bit number in AL. The main program will call this subroutine, store the result in two consecutive memory words, and stop.
Assume that SI and DI contain the signed 8-bit and bit numbers, respectively. Write a program using the X86 instructions to compare a source string of words pointed to by an offset of H in DS with a destination string pointed to by an offset H in DS.
Write a program using the X86 instructions to convert a word of text from upper case to lower case. Vranesic and S. Heuring, and H.
Patterson and J. A, Tanenbaum, Structured Computer Organization, 4th ed. Our goal is to introduce the reader to the fundamental issues related to the arithmetic operations and circuits used to support computation in computers. Our coverage starts with an introduction to number systems. In particular, we introduce issues such as number representations and base conversion. This is followed by a discussion on integer arithmetic. In this regard, we introduce a number of algorithms together with hardware schemes that are used in performing integer addition, subtraction, multiplication, and division.
Radices that are power of 2 are widely used in digital systems. These radices include binary base 2 , quaternary base 4 , octagonal base 8 , and hexagonal base The base 2 binary system is dominant in computer systems. In this case, decimal numbers ranging from 0 to 15 corresponding to binary to can be represented. Similarly, the largest unsigned number that can be obtained using 4 digits in base 4 is Fundamentals of Computer Organization and Architecture, by M.
In this case, decimal numbers ranging from 0 to corresponding to to can be represented. It is often necessary to convert the representation of a number from a given base to another, for example, from base 2 to base This can be achieved using a number of methods algorithms. An important tool in some of these algorithms is the div- ision algorithm. The basis of the division algorithm is that of representing an integer a in terms of another integer c using a base b.
Radix conversion is discussed below. Radix Conversion Algorithm A radix conversion algorithm is used to convert a number representation in a given radix, r1 , into another representation in a different radix, r2. Consider the conversion of the integral part of a number X, Xint. Repeating the division process on the quo- tient and retaining the remainders as the required digits until a zero quotient is obtained will result in the required representation of Xint in the new radix r2.
Using a similar argument, it is possible to show that a repeated multiplication of the fractional part of X Xf by r2 retaining the obtained integers as the required digits, will result in the required representation of the fractional part in the new radix, r2.
Therefore, the process may have to be terminated after a number of steps, thus leading to some acceptable approximation.
Example Consider the conversion of the decimal number A similar method can be used to obtain the fractional part through repeated multiplication : Fractional part 0. Therefore, the resultant representation of the number Negative Integer Representation There exist a number of methods for representation of negative integers. These include the sign-magnitude, radix complement, and diminished radix complement.
Although simple, the sign-magnitude representation is complicated when performing arithmetic opera- tions. In particular, the sign bit has to be dealt with separately from the magnitude bits. Since the two numbers carry different signs, then the result should carry the sign of the larger number in magnitude, in this case the The remaining 5-bit numbers are subtracted 2 to produce , that is, Radix Complement According to this system, a positive number is represented the same way as in the sign-magnitude.
Then each digit is complemented, hence the name radix complement to produce Since the number is positive, then it is represented as , the same as in the sign-magnitude case. Now, consider the addition of these two numbers. In this case, we add the corresponding bits without giving special treatment to the sign bit.
The results of adding the two numbers produces Table 4. Perform the Boolean complement of each bit including the sign bit ; 2.
Consider the fol- lowing two examples. This is because the result is less than the smallest value Notice that the original numbers are negative while the result is positive. This is because sub- traction is after all addition to the complement. Consider the following illustrative example. These three bits represent respectively the two current bits of the numbers A and B at position i and the carry bit from the previous bit position at position i 2 1.
The circuit should pro- duce two outputs, that is, si and ci representing respectively the sum and the carry, according to the following truth-table. The circuit used to implement these two functions is called a full-adder FA and is shown in Figure 4.
Addition of two n-bit numbers A and B can be carried out using n consecutive FAs in an arrangement known as a carry-ripple through adder CRT , see Figure 4. The n-bit CRT adder shown in Figure 4. Figure 4. The control input determines whether an add or a subtract operation is to be performed such that if the control input is 0 then an add operation is performed while if the control input is 1 then a subtract operation is performed.
This is because of the dependence of each stage on the carry output produced by the pre- vious stage. In order to speed up the addition process, it is necessary to introduce addition circuits in which the chain of dependence among the adder stages must be broken. A number of fast addition circuits exist in the lit- erature.
Among these the carry-look-ahead CLA adder is well known. The CLA adder is introduced below. Consider the CRT adder circuit. Now, we can write Figure 4. The sequence of carry outputs shows total independence among the different car- ries broken carry chain.
There are basically three blocks in a CLA. The third block is used to generate all the sum outputs. In Figure 4. The reader is encouraged to complete the design see the Chapter Exercises.
A number of methods exist for performing multiplication. Some of these methods are discussed below. The Paper and Pencil Method for Unsigned Numbers This is the simplest method for performing multiplication of two unsigned numbers.
The method is illus- trated through the example shown below. Example Consider the multiplication of the two unsigned numbers 14 and The process is shown below using the binary representation of the two numbers. Each cell computes a given partial product. What characterizes this method is the need for adding n partial products regard- less of the values of the multiplier bits. It should be noted that if a given bit of the multiplier is 0, then there should be no need for computing the corresponding partial product.
The following method makes use of this observation. The Add-Shift Method In this case, multiplication is performed as a series of n conditional addition and shift operations such that if the given bit of the multiplier is 0 then only a shift operation is performed, while if the given bit of the multiplier is 1 then addition of the partial products and a shift operation are performed.
The follow- ing example illustrates this method. Example Consider multiplication of the two unsigned numbers 11 and The process is shown below in a tabular form. An n-bit adder is used to add the contents of registers A and M. In order to speed up the multiplication operation, a number of other techniques can be used.
These techniques are based on the observation that the larger the number of consecutive zeros and ones, the fewer partial products that have to be gen- erated. A group of consecutive zeros in the multiplier requires no generation of new partial product.
A group of k consecutive ones in the multiplier requires the gener- ation of fewer than k new partial products. No action is needed if the values are 00 or In all four cases, an arithmetic shift right oper- ation on the concatenation of AQ is performed. The whole process is repeated n times n is the number of bits in the multiplier.
No Yes Done Figure 4. The steps needed are tabulated below. A control circuitry is also required to perform the ASR AQ and to issue the appropriate signals needed to control the number of cycles.
This last situation can be improved if three rather than two bits are inspected at a time. Division Among the four basic arithmetic operations, division is considered the most complex and most time consuming. In its simplest form, an integer division oper- ation takes two arguments, the dividend X and the divisor D. It produces two outputs, the quotient Q and the remainder R.
A number of complications arise when dealing with division. We will start by showing the division algorithm assuming that all values involved, that is, divided, divisor, quotient, and remainder are interpreted as frac- tions. The process is also valid for integer values as will be shown later.
In each step, the remainder should be compared with the divisor D. The process is illustrated in the following table. Now we show the validity of the above process in the case of integer values. We offer the following illustrative example. These are correct values. A hardware structure for binary division is shown in Figure 4. A control logic is used to perform the required shift left operation see Exercises.
This required restoring the previous value by adding back the subtracted value restoring division. The alternative is to use a non-restoring division algorithm: Step 1: Do the following n times 1. Step 2: If the sign of A is 1, add D to A. Example Figure 4. If the value stored in S is 0, the number is positive and if the value stored in S is 1, the number is negative.
The exponent in the above example, can only represent positive numbers 0 through To simplify performing operations on FP numbers and to increase their precision, they are always represented in what is called normalized forms.
An FP number is said to be normalized if the leftmost bit of the mantissa is 1. Therefore, among the three above possible representations for 1. Therefore, before adding two FP numbers, their exponents must be equalized, that is, the mantissa of the number that has smaller magnitude of exponent must be aligned. Compare the magnitude of the two exponents and make suitable alignment to the number with the smaller magnitude of exponent. Perform normalization by shifting the resulting mantissa and adjusting the resulting exponent.
Example Consider adding the two FP numbers 1. Alignment: 1. Addition: Add the two numbers to get A general algorithm for multiplication of FP numbers consists of three basic steps. These are: 1. Compute the exponent of the product by adding the exponents together.
Multiply the two mantissas. Multiply mantissas: 1. The product is A general algorithm for division of FP numbers consists of three basic steps: 1. Compute the exponent of the result by subtracting the exponents.
Divide the mantissa and determine the sign of the result. Normalize and round the resulting value, if necessary. Divide the mantissas: 1. The result is Division of two FP numbers can be illustrated using the schematic shown in Figure 4. These are the basic and the extended formats. The single-precision format is bit and the double-precision is bit. The single extended format should have at least 44 bits and the double extended format should have at least 80 bits. The 8-bit exponent allows for any of combinations.
Among these, two com- binations are reserved for special values: 1. This results in a total length of at least 44 bits. The single extended format is used in calculating intermediate results. The format is shown in Figure 4. Similar to the single-precision format, the extreme values of e 0 and are reserved for the same purpose. Our discussion started with an introduction to number representation and radix con- version techniques. We then discussed integer arithmetic and, in particular, we dis- cussed the four main operations, that is, addition, subtraction, multiplication, and division.
In each case, we have shown basic architectures and organization. Compute the decimal value of the binary number if the given number represents unsigned integer. Repeat if the number represents sign-magnitude integer. Divide each of the following pairs of signed 20 s complement numbers using both the restoring and the nonrestoring algorithms. Design a BCD adder using a 4-bit binary adder and the least number of logic gates.
The adder should receive two 4-bit numbers A and B and should pro- duce 4-bit sum and a carry output. Compute the delay and the area in terms of the number of logic gates required. Compare the longest path delay from input to output of a bit adder using 4-bit CLA adder blocks in a multilevel architecture with that of a bit CRT adder.
Assume that a gate delay is given by Tg. Complete the logic design of the array multiplier shown in Figure 4. Design the control logic shown in Figure 4. Provide a complete logic design for the Control Logic indicated in Figure 4. Heuring and H.
Israel, Computer Arithmetic Algorithms, 2nd ed. Peters, Ltd. In this chapter, we focus our attention on the main component of any computer system, the central processing unit CPU. In what follows, the reader will be introduced to the organization and main operations of the CPU. The register set differs from one computer architecture to another.
It is usually a combination of general-purpose and special- purpose registers. General-purpose registers are used for any purpose, hence the name general purpose. For example, the program counter PC is a special-purpose register that is used to hold the address of the instruction to be executed next. Another example of special-purpose registers is the instruction register IR , which is used to hold the instruction that is currently executed.
The ALU provides the cir- cuitry needed to perform the arithmetic, logical and shift operations demanded of the instruction set. In Chapter 4, we have covered a number of arithmetic oper- ations and circuits used to support computation in an ALU. The control unit is the entity responsible for fetching the instruction to be executed from the main memory and decoding and then executing it.
Figure 5. The next instruction to be executed, whose address is obtained from the PC, is fetched from the memory and stored in the IR. The instruction is decoded. Operands are fetched from the memory and stored in CPU registers, if needed. The instruction is executed. Results are transferred from CPU registers to the memory, if needed.
The execution cycle is repeated as long as there are more instructions to execute. A check for pending interrupts is usually included in the cycle. When an interrupt request is encountered, a transfer to an interrupt handling routine takes place. Interrupt handling routines are programs that are invoked to collect the state of the currently executing program, correct the cause of the interrupt, and restore the state of the program.
These micro-orders are individual control signals sent over dedicated control lines. For example, let us assume that we want to execute an instruction that moves the contents of register X to register Y. Let us also assume that both registers are connected to the data bus, D. The control unit will issue a con- trol signal to tell register X to place its contents on the data bus D.
After some delay, another control signal will be sent to tell register Y to read from data bus D. The acti- vation of the control signals is determined using either hardwired control or micropro- gramming. These concepts are explained later in this chapter. Section 5. In Sec- tion 5. CPU instruction cycle and the control unit will be covered in Sections 5.
Differ- ent computers have different register sets. They differ in the number of registers, reg- ister types, and the length of each register.
They also differ in the usage of each register. General-purpose registers can be used for multiple purposes and assigned to a variety of functions by the programmer. In some cases, some registers are used only to hold data and cannot be used in the calculations of operand addresses.
The length of a data register must be long enough to hold values of most data types. Some machines allow two contiguous registers to hold double-length values. Address registers may be dedicated to a particular addressing mode or may be used as address general purpose. Address registers must be long enough to hold the largest address.
The number of registers in a particular architecture affects the instruction set design. A very small number of registers may result in an increase in memory references. These bits are set by the CPU as the result of the execution of an operation. The status bits can be tested at a later time as part of another operation.
A write signal is issued by the CPU. A read signal is issued by the CPU. Instruction Fetching Registers Two main registers are involved in fetching an instruction for execution: the pro- gram counter PC and the instruction register IR.
The PC is the register that con- tains the address of the next instruction to be fetched. The fetched instruction is loaded in the IR for execution. After a successful instruction fetch, the PC is updated to point to the next instruction to be executed. In the case of a branch operation, the PC is updated to point to the branch target instruction after the branch is resolved, that is, the target address is known.
Some architec- tures contain a special program status word PSW register. These indicators are typically for arithmetic operations, interrupts, memory protection information, or processor status. Special-Purpose Address Registers Index Register As covered in Chapter 2, in index addressing, the address of the operand is obtained by adding a constant to the content of a register, called the index register.
The index register holds an address displacement. Index addressing is indi- cated in the instruction by including the name of the index register in parentheses and using the symbol X to indicate the constant to be added.
Segment Pointers As we will discuss in Chapter 6, in order to support segmen- tation, the address issued by the processor should consist of a segment number base and a displacement or an offset within the segment. A segment register holds the address of the base of the segment. These are the Push and the Pop operations. In the stack push operation, the SP value is used to indicate the location called the top of the stack.
After storing pushing this value, the SP is incremented in some architectures, e. X86, the SP is decremented as the stack grows low in memory. The next 6 — 11 bits are identical to those introduced in the Table 5. The objects in this heap can be quickly accessed with a single load or store instruction. The data section, which is also called the datapath, contains the registers and the ALU.
The datapath is capable of performing certain operations on data items. The control section is basi- cally the control unit, which issues control signals to the datapath. Internal data movements are performed via local buses, which may carry data, instructions, and addresses. Internal data movement among registers and between the ALU and registers may be carried out using different organizations including one-bus, two-bus, or three-bus organizations.
Dedicated datapaths may also be used between components that transfer data between them- selves more frequently. For example, the contents of the PC are transferred to the MAR to fetch a new instruction at the beginning of each instruction cycle. Hence, a dedicated datapath from the PC to the MAR could be useful in speeding up this part of instruction execution. Since a bus can handle only a single data movement within one clock cycle, two-operand operations will need two cycles to fetch the operands for the ALU.
Additional registers may also be needed to buffer data for the ALU. This bus organization is the simplest and least expensive, but it limits the amount of data transfer that can be done in the same clock cycle, which will slow down the overall performance. Two-Bus Organization Using two buses is a faster solution than the one-bus organization.
In this case, gen- eral-purpose registers are connected to both buses. Data can be transferred from two different registers to the input point of the ALU at the same time. Therefore, a two- operand operation can fetch both operands in the same clock cycle. An additional buffer register may be needed to hold the output of the ALU when the two buses are busy carrying the two operands.
In some cases, one of the buses may be dedicated for moving data into registers in-bus , while the other is dedicated for transferring data out of the registers out-bus.
In this case, the additional buffer register may be used, as one of the ALU inputs, to hold one of the operands. The ALU output can be connected directly to the in-bus, which will transfer the result into one of the registers.
Three-Bus Organization In a three-bus organization, two buses may be used as source buses while the third is used as destination. Each of the two out-buses is connected to an ALU input point. The output of the ALU is connected directly to the in-bus.
As can be expected, the more buses we have, the more data we can move within a single clock cycle. However, increasing the number of buses will also increase the complexity of the hardware. As long as there are instructions to execute, the next instruction is fetched from main memory. At the completion of the instruction execution, a test is made to determine whether an interrupt has occurred.
An interrupt handling routine needs to be invoked in case of an interrupt. A group of control signals must be enabled in a prescribed sequence to trigger the execution of a micro- operation. In this section, we show the micro-operations that implement instruction fetch, execution of simple arithmetic instructions, and interrupt handling. Fetch Instructions The sequence of events in fetching an instruction can be summarized as follows: 1.
The value in the PC is incremented. This operation can be done in parallel with a memory access. As a result of a memory read operation, the instruction is loaded into the MDR. Let us consider the one-bus datapath organization shown in Fig. We will see that the fetch operation can be accomplished in three steps as shown in the table below, where t0 , t1 , t2. This addition can be executed as follows: 1. The output of the ALU is transferred to R0. As a result of memory read operation, the contents of X are loaded into MDR.
The contents of MDR are added to the contents of R0. Using the one-bus datapath shown in Figure 5. Interrupt Handling After the execution of an instruction, a test is performed to check for pending inter- rupts.
If there is an interrupt request waiting, the following steps take place: 1. The following table shows the sequence of events, where t1 , t2 , t3. Control buses generally carry signals between the control unit and other computer components in a clock-driven manner. A sequence of steps t0 , t1 , t2 ,. Step information generated by a logic circuit module is used with other inputs to generate control signals.
There are mainly two different types of control units: microprogrammed and hardwired. In microprogrammed control, the control signals associated with oper- ations are stored in special memory units inaccessible by the programmer as control words. Clearly hardwired control is faster than microprogrammed control. However, hardwired control could be very expensive and complicated for complex systems.
Hardwired control is more econ- omical for small control units. It should also be noted that microprogrammed control could adapt easily to changes in the system design. We can easily add new instruc- tions without changing hardware.
Hardwired control will require a redesign of the entire systems in the case of any change. Example 1 Let us revisit the add operation in which we add the contents of source registers R1 , R2 , and store the results in destination register R0. We have shown earlier that this operation can be done in one step using the three-bus datapath shown in Figure 5. Let us try to examine the control sequence needed to accomplish this addition at step t0.
First we need to select the source registers and the destination register, then we select Add as the ALU function to be performed. The following table shows the needed step and the control sequence.
Externally visual attributes, here in computer science, mean the way a system is visible to the logic of programs not the human eyes! Organization of computer system is the way of practical implementation which results in realization of architectural specifications of a computer system. In more general language, Architecture of computer system can be considered as a catalog of tools available for any operator using the system, while Organization will be the way the system is structured so that all those cataloged tools can be used, and that in an efficient fashion.
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